Intel used the Hot Chips 2023 program to present the next generation of its Xeon processors, codenamed Sierra Forest and Granite Rapids. This will be the very first generation of Xeon processors with different core designs: the new Efficient-core (E-core) architecture and existing Performance-core (P-core) architecture.
The new processors will be significantly beefier than the previous generation, codenamed Sapphire Rapids. They will include approximately 144 cores and stress higher memory and I/O bandwidth efficiency, two locations where Xeon has actually dragged AMD’s Epyc processors.Intel declares the Sierra
Forest processors with E-cores will offer up to 2.5 times much better rack density and 2.4 times greater efficiency per watt than Sapphire Rapids, while the Granite Rapids processors with P-cores will offer 2 to 3 times the efficiency in blended AI workloads, which it associates in part to an enhancement in memory bandwidth of approximately 2.8 times.P-core is high performance and meant for optimum processing, while E-core is a lower-level processing core for less compute-intensive jobs. Not every computer process needs a high-performance CPU, so utilizing a P-core on something like file and print was overkill. Conversely, E-core uses less power.Sierra Forest and Granite Rapids likewise integrate a chiplet design instead of one monolithic piece of silicon. This will allow Intel to blend and match P-core and E-core designs for custom silicon.Granite Rapids follows Sapphire Rapids as a conventional Xeon data center processor. Each P-core features 2MB of L2 cache and 4MB of L3. Intel did not divulge the core count for Granite Rapids, however it did state it will support as much as 8 sockets in a single server. The architecture for the P-cores supports something Intel calls Advanced Matrix Extensions(AMX) for deep learning processing, with FP16 acceleration. FP16 is a standard extension for AI processing, and a lot of AI processors target FP16.Sierra Forest’s E-cores appear implied to take on the Arm processors from Ampere, Fujitsu, and other makers of Arm-based server silicon. In this case, Intel did reveal the core count: up to 144 cores optimized for power efficiency. Sierra Forest is suggested for single -and dual-socket systems and has a TDP of around 200W, which these days is low power. The Sierra Forest processors likewise feature much beefier memory controllers, supporting 12 channels(a good increase compared to eight channels in Sapphire Rapids )of DDR5-6400 memory and 136 lanes of PCIe 5.0/ CXL
2.0 interfacing. In addition to the DDR memory, the fifth-generation Xeon’s will support the brand-new MCR memory Intel developed that offers 30%to 40%more memory bandwidth than standard DIMMs.The fifth-generation Xeon chips are planned for release next year.Hot Chips is an annual event that uses a very deep technical dive into all things electrical engineering. It’s held each August at Stanford University, which is the alma mater of numerous substantial chip engineers, including Intel’s Pat Gelsinger and Nvidia’s Jensen Huang.
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